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1 full-featured, dimmable ac mains led driver with pfc ISL1902 the ISL1902 is a high-performance , critical conduction mode (crcm), single-ended controll er used for single-stage conversion of the ac mains to a constant current source with power factor correction (pfc). this controller may be used in virtually any single-ended topolo gy, isolated or non-isolated, including boost, sepic, flyback, and forward converters. operation in crcm allows near zero-voltage switching (zvs) for improved efficiency while maximizing magnetic core utilization. the ISL1902 is compatible with both leading and trailing edge modulated ac mains dimmers as well as analog signal and ambient light sensor controlled dimming methods. the led string may be dimmed either by modulation of the dc current or pwm dimming. in-rush current limiting minimizes current spikes caused by leading edge dimmers and prevents dimmer malfunction when one or more led fixtures are connected. two control loops are provided to improve transient response since one loop must have restri cted bandwidth to allow pfc. the second control loop may be configured for higher bandwidth to respond to input transients quickly and prevent them from propagating to the load and appearing as flashing/flickering. the ISL1902 led driver controller provides all of the features required for high-performance dimmable led ballast designs. applications ? industrial and commercial led lighting ? architectural lighting led drivers ? ac or dc input led ballasts features ? excellent led current regulation over line, load, and temperature ? 0 - 100% dimming with leading-edge (triac) and trailing-edge dimmers ? analog control signal dimming ? configurable for pwm or dc current dimming control of leds ? dual control loops for pfc and fast transient response ? compatible with ambient light sensors for uniform lamp-to-lamp performance ? power factor correction for up to 0.995 power factor and less than 20% harmonic content ? critical conduction mode (crcm) operation for quasi-resonant high efficiency performance ? supports universal ac mains input ? active pre-load to eliminate power-off ?afterglow? ? offref feature sets dimming turn-off-threshold to improve fixture performance matching ? in-rush protection control for each ac half-cycle minimizes audible noise and eliminates dimmer resonance ? input or output overvoltage protection (ovp) ? over-temperature protection (otp) ? bias supply under voltage lockout (uvlo) ? -40c to +125c operation ? pb-free (rohs compliant) figure 1. typical applicat ion - dimming performance figure 2. typical application - power factor 0 100 200 300 400 500 600 700 800 0 20 40 60 80 100 ac conduction angle (%) led current (ma) 0.90 0.92 0.94 0.96 0.98 1.00 80 130 180 230 input voltage (v rms ) power factor caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. march 20, 2013 fn7981.2
ISL1902 2 fn7981.2 march 20, 2013 pin configuration ISL1902 (24 ld qsop top view vdd preload offref vref iout cs+ cs- refin lpout oc fb2 fb1 out inrush gnd ac ovp lref ramp verr deladj pwmout lout lfb 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 pin descriptions pin # symbol description 1 vdd vdd is the power connection for the ic. to optimize noise immunity, bypass vdd to gnd with a ceramic capacitor as close to the vdd and gnd pins as possible. 2 preload the output control signal to drive an external fet placed in parallel with th e led load. this feature allows the output capacitor to be quickly discharged to prevent continued low level illumination of the leds due to stored energy in the output capacitor. 3 offref sets the reference level to disable the driver at light lo ading. the turn-off reference can be set at any level between 0v and 0.6v, corresponding to 0% to 100% of output loading. this feature is normally used in triac-based wall dimmer applications to disable the output before the dimmer becomes unstable due to insufficient ho lding current. offref triggers preload to discharge the output capacitance with an external fet. 4 vref the 5.40v reference voltage output having 100mv tolerance ov er line, load and operating temperature. bypass to gnd with a 0.1f to 3.3f low esr capacitor. 5 iout the output of the differential current sensing circuit. a pair of resistors and capacitors is placed on this output to for m two low pass filters. iout creates the current feedback signals for the control loop and is normally filtered and scaled prior to inputing a t fb1 and fb2 through separate input resistors to allow for different bws. 6, 7 cs+, cs- the differential inputs for th e current sense circuit. this circuit generates a dc feedback signal for the control loop as well as the input to the crcm circuit to determine the critical conduction operating point. cs has a common mode range of -0.3v to 0.5v an d a differential input range of 0v to1.5v 8 refin the reference voltage input that sets the control loop refe rence. normally connected to lp out or an external control refe rence. 9 lpout output of the digital low-pass filter. the output ranges from 0v to 0.5v in proportion to the ac conduction angle. this o utput may be used as is or manipulated (such as when us ed with an external light sensor or temperature monitor) and applied to refin to be u sed as the reference for the control loop. 10 oc this is the input to the peak overcurrent comparator. the ov ercurrent comparator threshold is set at 600mv nominal. peak oc p is required for cycle-by-cycle protection. it also protects against low ac line conditions. ocp includes leading-edge-blanking (le b), which blocks the signal at the beginning of the out pulse for the dura tion of the blanking period, and also while the out pulse is lo w. 11, 12 fb2, fb1 fbx is the inverting input to the error amplifier (e as). the current feedback signal is applied to ea1 and ea2. e a1 is the primary error amplifier and is used for steady state operation. ea2 is the seco ndary control loop for operation during transients. normally e a1 is configured for low bandwidth operation, about 20hz, to obtain powe r factor correction. ea2 is configured for higher bw to respo nd to transients. both error amplifiers are externally compensated to give the user complete flexibility. 13 deladj sets delay before a new switching cycles starts. this ad justment allows the user to delay the next switching cycle unti l the switching fet drain-source voltage reaches a minimum value to allow quasi- zvs (zero voltage switching) operation. a resistor to ground programs the delay. pulling deladj to vref disables the crcm oscillator. 14 verr output of the error amplifiers and the control voltage inpu t to the inverting input of the pwm comparator. verr requires an external pull-up resistor to vref. 15 ramp this is the input for the sawtooth waveform for the pwm comp arator. using an rc from vref, a sawtooth waveform is created for use by the pwm. it is compared to the error amplifier output, ve rr, to create the pwm control signal. the ramp pin is shorted t o gnd at the termination of the pwm signal. 16 lfb the inverting input to the uncommitted linear amplifier.
ISL1902 3 fn7981.2 march 20, 2013 17 lref the non-inverting input to the uncommitted linear amplifier. 18 lout output of the uncommitted linear amplifier. 19 ovp input to detect an overvoltage (ov) condition on the output with a nominal threshold of 1.5v. since the control variable i s output current, a fault that results in an open circuit will cause exce ssive output voltage. the circui t hysteresis is a switched curr ent source that is active when the ov threshold is exceeded. 20 ac input to sense ac voltage presence and amplitude. a resistor divider from line and neutral/line and circuit ground is used to detect the ac voltage. 21 gnd signal and power ground connections for this device. due to high peak currents and high fr equency operation, a low impedan ce layout is necessary. ground planes and short traces are highly recommended. 22 inrush output to drive an isolation transf ormer to control an inrush current limiting device. typically this would be a triac, back-to-back fets, or anti-parallel scrs, etc. the output is a 50% duty cycle ~80khz square-wave capable of sourcing 10ma. the output is enabled i n conjunction with an ac outage (such as from a wall dimmer). op eration is delayed for ~150s after ac returns and is enabled unt il ac is interrupted again. the inrush output is also inhibited during normal ac zero -crossing even at full conduction angle. 23 pwmout the pwm gate drive output for led dimming . the output level is clamped to ~12v for v dd greater than 12v. pwmout has pull-down capability when uvlo is active or when the ic is not biased. this output is used to drive the dimming fet in series with the le d string. the pwm operates at ~310hz. 24 out the gate drive output for the external power fet. out is capable of sourcing and sinking 1a @ v dd = 8v. the output level is clamped to ~12v for v dd greater than 12v. out has pull-down capability when uvlo is active or when the ic is not biased. pin descriptions (continued) pin # symbol description ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL1902faz isl 1902faz -40 to +125 24 ld qsop m24.15 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL1902 . for more information on msl please see tech brief tb363 .
ISL1902 4 fn7981.2 march 20, 2013 functional block diagram - ISL1902 out pwm comparator pwm latch + - s r q q + - ramp ac crcm detector f max clamp 200mv + - master oscillator lpout refin duty cycle to voltage converter low pass filter inrush 150us one shot inrush control circuit + - - deladj + - triangle wave generator clk - + pwmout verr 600 mv vref lout lfb lref dimming pwm + - ea1 crcm oscillator/pwm/error amplifiers linear amplifier oc leading edge blanking fb1 quasi-zvs delay iout refinbuff + - ea2 fb2 primary oc clk delayed ac-p f min clamp peak detector 1/5 ss/5 1/5 verr/5 pwm verr ac present 0-xing blanking _ + + bias and reference generator gnd vdd uvlo + - vref otp shutdown 150 - 170 c bias/uvlo/otp + - cs- cs+ differential isense iout no ac counter clk rst carry - + preload offref minimum dimming level control 0.25 v ss low fault latch + - s r q q ss + - 300 ms soft start enable + - 1.50 v bg inhibit inhibit verr clamp ovp ref reference ss ac-present ss refinbuff reference ss buffer q q 350 s one shot q q ac detection soft-start/por/ovp
ISL1902 5 fn7981.2 march 20, 2013 typical application - sepic to pology with pwm dimming and ambient light compensation ambient light sensor emi filter ac mains dimmer 13 14 15 16 17 18 19 20 21 22 23 24 1 2 4 3 5 6 7 8 9 10 11 12 cs+ inrush offref pwmout vref out vdd oc ovp preload ac iout ramp lout lref lfb lpout refin cs- gnd fb2 fb1 deladj verr ISL1902
ISL1902 6 fn7981.2 march 20, 2013 typical application - isolated flybac k with pwm dimming and ambient light compensation 9 10 11 12 13 14 15 16 1 2 4 3 5 6 7 8 isl1904 cs+ dhc offref pwmout vref out vdd oc ovp ac iout ramp gnd fb deladj verr emi filter ac mains dimmer ambient light sensor 13 14 15 16 17 18 19 20 21 22 23 24 1 2 4 3 5 6 7 8 9 10 11 12 cs+ inrush offref pwmout vref out vdd oc ovp preload ac iout ramp lout lref lfb lpout refin cs- gnd fb2 fb1 deladj verr ISL1902
ISL1902 7 fn7981.2 march 20, 2013 typical application - non-isolated flyb ack with pwm dimming and ambient light compensation 13 14 15 16 17 18 19 20 21 22 23 24 1 2 4 3 5 6 7 8 9 10 11 12 cs+ inrush offref pwmout vref out vdd oc ovp preload ac iout ramp lout lref lfb lpout refin cs- gnd fb2 fb1 deladj verr ISL1902 ac mains dimmer emi filter ambient light sensor
ISL1902 8 fn7981.2 march 20, 2013 absolute maximum rating s thermal information supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +28.0v out, pwmout, inrush . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to vdd signal pins (except cs-) . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to v ref + 0.3v signal pin cs- . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.6v to v ref + 0.3v vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .gnd - 0.3v to 6.0v peak out current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.0a peak pwmout current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.0a esd classification human body model (per mil-std-883 method 3015.7) . . . . . . . . 1500v machine model (per eiaj ed-4701 method c-111) . . . . . . . . . . . . . 150v charged device model (per eos/esd ds5.3, 4/14/93). . . . . . . . . 750v latchup (per jesd-78b; class 2, level a. . . . . . . . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 24 lead qsop (notes 4, 5) . . . . . . . . . . . . . 78 34 maximum junction temperature . . . . . . . . . . . . . . . . . . . .-55c to +150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c supply voltage range (typical). . . . . . . . . . . . . . . . . . . . . . . 9vdc to 20vdc caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 5. for jc , the ?case temp? location is taken at the package top center. 6. all voltages are with respect to gnd. electrical specifications recommended operating conditions unless otherwise noted. refer to the block diagram on page 4 and typical application schematics starting on page 5. v dd = 17v, r ramp = 54k , c ramp = 470pf, t a = -40c to +125c, typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +125c. parameter test conditions min (note 7) typ max (note 7) units supply voltage supply voltage 26 v start-up current, idd v dd = 5.0v 100 200 a operating current, idd r load , c out = 0 10 14.5 ma uvlo start threshold 14.8 15.5 16.1 v uvlo stop threshold 6.80 7.10 7.50 v hysteresis 7.50 8.30 9.30 v reference voltage (vref) overall accuracy i vref = 0ma to -10ma, 8v < v dd < 26v 5.30 5.40 5.50 v long term stability t a = +125c, 1000 hours (note 8) 10 25 mv operational current (source) 8v < v dd < 26v -10 ma current limit v ref = 5.00v, 8v < v dd < 26v -15 -100 ma load capacitance (note 8) 0.1 3.3 f peak current sense (oc) current limit threshold verr = vref, ramp = 0v 577 600 623 mv leading edge blanking (leb) duration (note 8) 70 120 150 ns oc to out delay + leb t a = +25c 110 170 200 ns input bias current v oc = 0.3v -1.0 1.0 a ramp ramp sink current device impedance i ramp = 10ma 20 ramp to pwm comparator offset 190 235 287 mv input bias current v ramp = 0.3v -1.0 1.0 a
ISL1902 9 fn7981.2 march 20, 2013 pulse width modulator pwm restart delay range 8v < v dd < 26v 0.2 2.0 s pwm restart cycle delay rdeladj = 20.0k , 8v < v dd < 26v 240 280 320 ns rdeladj = 210k , 8v < v dd < 26v 2.00 2.20 2.40 s maximum frequency clamp r ramp = 100 , ramp = 2v, 8v < v dd < 26v 0.7 1.0 1.2 mhz minimum frequency clamp r ramp = 23k , 8v < v dd < 26v 20 25 31 khz minimum duty cycle 8v < v dd < 26v, comp = 0v 0 % minimum non-zero output duration 8v < v dd < 26v 70 100 130 ns zero current (crcm) detector threshold, falling 8v < v dd < 26v 728 mv verr to pwm gain 8v < v dd < 26v 0.200 v/v ss to pwm gain 8v < v dd < 26v 0.222 v/v error amplifiers (ea1 and ea2) input common mode (cm) range (note 8) 03.4 v gbwp (note 8) 1.9 mhz verr vol ea1 i verr = 6ma, 8v < v dd < 26v 0.950 v verr vol ea2 i verr = 4ma, 8v < v dd < 26v 0.950 v verr voh i verr = 1ma (ext. pull-up) ss complete 3.90 4.00 4.20 v open loop gain (note 8) 70 db offset voltage (vos) 8v < v dd < 26v -7.5 7.5 mv input bias current, fb1 refin = 0.5v, fb1 = 2.0v, fb2 = 0v, 8v < v dd < 26v -1.0 1.0 a input bias current, fb2 refin = 0.5v, fb2 = 2.0v, fb1 = 0v, 8v < v dd < 26v -1.0 1.0 a differential current sense (cs+, cs-) iout amplifier gain cs- = 0v, cs+ = 0.1v, 0.3v, 8v < v dd < 26v 2.910 2.970 3.030 v/v common mode (cm) input range 8v < v dd < 26v -0.30 0.50 v differential input range 8v < v dd < 26v 01.5 v offset voltage (vos) 8v < v dd < 26v -36 48 mv gbwp (note 8) 8 mhz slew rate (note 8) 45 v / s input bias current cs- = 0v, 1.0v cs+ = 1.0v, 1.5v 8v < v dd < 26v -1.0 1.0 a iout high level output voltage (voh) v iout at 0a - v iout at -100a, 8v < v dd < 26v 0.1 v iout low level output voltage (vol) v iout at 100a, 8v < v dd < 26v 0.1 v ac detector input bias current 8v < v dd < 26 -50 50 na detection threshold, falling ac peak = 100mv, 8v < v dd < 26v 4.5 20 40.5 mv detection threshold hysteresis 8v < v dd < 26v 6 mv input operating range 8v < v dd < 26v 04.00 v electrical specifications recommended operating conditions unless otherwise noted. refer to the block diagram on page 4 and typical application schematics starting on page 5. v dd = 17v, r ramp = 54k , c ramp = 470pf, t a = -40c to +125c, typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +125c. (continued) parameter test conditions min (note 7) typ max (note 7) units
ISL1902 10 fn7981.2 march 20, 2013 clamp voltage i acdetect = 1.0ma 6.8 7.2 7.6 v inrush high level output voltage (voh) v inrush at 0ma - v inrush at -10ma, v dd = 8v operating 1.00 v low level output voltage (vol) v inrush = 10ma, v dd = 8v operating 1.00 v inrush duration (see t delay fig. 10) 8v < v dd < 26v 140 180 220 s output clamp voltage v dd = 20v, i inrush = -10a 10.5 12 13.4 v unbiased output voltage clamp v dd = 6v, i load = 3ma 2.3 v low pass filter high level output voltage (voh) v lpout at 0a - v lpout at -100a, 8v < v dd < 26v 0.1 v low level output voltage (vol) v lpout at 100a, 8v < v dd < 26v 0.1 v output range 00.50 v lpout vs ac conduction angle i lpout = 0a, f = 120hz (rectified), 8v < v dd < 26v 485 514 543 mv duty cycle ( ) = 98% duty cycle ( ) = 75% 273 300 323 mv duty cycle ( ) = 50% 110 130 148 mv duty cycle ( ) = 25% 16 30 41 mv duty cycle ( ) = 10% 0 1 9 mv refin input common mode (cm) range 0vref-1 v input bias current refin = 4.4v -1.0 1.0 a offset voltage (vos), combined fbx + refin at ea 8v < v dd < 26v, see fig. 11 -11 11 mv linear amplifier input offset (vos) lfb = lout, lref = 0.5v -4 4 mv high level output voltage (voh) i lout = -1ma, lfb = 0v, lref = vref (voh at 0ma - voh at -1ma) 1.0 v low level output voltage (vol) i lout = 8ma, lfb = vref, lref = 0v 1.0 v input common mode (cm) range 0vref v output operating range 0.3 4.3 v gbwp (note 8) 1 mhz open loop gain (note 8) 85 db input bias current lref, lfb lref = 1.0v, lfb = 1.0v -1.0 1.0 a output pull-down impedance v dd = 6.0v, i lout = 100 a 10 k ? soft-start duration 282 370 483 ms reference soft-start initial step 21 mv offref input bias current offref = 0.5v -1.0 1.0 a electrical specifications recommended operating conditions unless otherwise noted. refer to the block diagram on page 4 and typical application schematics starting on page 5. v dd = 17v, r ramp = 54k , c ramp = 470pf, t a = -40c to +125c, typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +125c. (continued) parameter test conditions min (note 7) typ max (note 7) units
ISL1902 11 fn7981.2 march 20, 2013 operating range (excluding offset) 00.5 v threshold hysteresis 48 62 76 mv threshold offset 78 104 129 mv ac dropout disable delay 32 ms preload voh i load = 0ma vref v preload vol i load = 1ma 1.00 v out high level output voltage (voh) v out at 0ma - v out at -100ma, v dd = 8v operating 0.35 1.2 v low level output voltage (vol) v out at 100ma, v dd = 8v operating 0.7 1.2 v rise time c load = 2.2nf, v dd = 8v, t 90% - t 10% 35 55 ns fall time c load = 2.2nf, v dd = 8v, t 10% - t 90% 20 40 ns output clamp voltage v dd = 20v, i load = -10a 10.5 12.0 13.4 v unbiased output voltage clamp v dd = 6v, i load = 5ma 1.9 v pwmout high level output voltage (voh) v out at 0ma - v out at -10ma, v dd = 8v operating 0.8 1.2 v low level output voltage (vol) v out at 10ma, v dd = 8v operating 0.8 1.2 v rise time c load = 1nf, v dd = 8v operating, t 90% - t 10% 130 240 ns fall time c load = 1nf, v dd = 8v operating, t 10% - t 90% 130 240 ns output voltage clamp v dd = 20v, i load = -10a 10.5 12.0 13.4 v unbiased output voltage clamp v dd = 6v, i load = 3ma 1.9 v frequency 291 320 349 hz maximum duty cycle refin = 0.5v 100 % minimum on-time refin = 0v 80 s ovp ovp threshold 1.46 1.50 1.54 v ovp hysteresis 15 20 25 a input bias current ovp = 1.0v -1.0 1.0 a ovp clamp voltage i ovp = 5ma 5.4 7.0 v thermal protection thermal shutdown (note 8) 150 160 170 c hysteresis (note 8) 25 c notes: 7. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. 8. limits established by characteriza tion and are not production tested. electrical specifications recommended operating conditions unless otherwise noted. refer to the block diagram on page 4 and typical application schematics starting on page 5. v dd = 17v, r ramp = 54k , c ramp = 470pf, t a = -40c to +125c, typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +125c. (continued) parameter test conditions min (note 7) typ max (note 7) units
ISL1902 12 fn7981.2 march 20, 2013 typical performance curves figure 3. reference voltage vs temperature f igure 4. lpout vs ac signal duty cycle figure 5. delay vs deladj resistance figure 6. pwmout duty cycle vs refin -40 -25 -10 5 20 35 50 65 80 95 110 125 0.996 0.997 0.998 0.999 1.000 1.001 temperature (c) normalized v ref 0 102030405060708090100 0 100 200 300 400 500 ac conduction angle (% duty cycle 120hz) lpout (mv) 0 25 50 75 100 125 150 175 200 225 0 0.5 1.0 1.5 2.0 2.5 delay resistance (k ? ) delay time (s) 0 20 40 60 80 100 0 50 100 150 200 250 300 350 400 450 500 refin (mv) pwmout duty cycle (%) test waveforms and circuits figure 7. rise/fall time test circuit figure 8. rise/fall times 13 14 15 16 17 18 19 20 21 22 23 24 1 2 4 3 5 6 7 8 9 10 11 12 cs+ inrush offref pwmout vref out vdd oc ovp preload ac iout ramp lout lref lfb lpout refin cs- gnd fb2 fb1 deladj verr ISL1902 8v* 1nf 2.2nf 470pf 54k 0 to 1v 120hz *vdd set to 8v after exceeding uvlo start threshold 0.1f 5k t r t f 90% 10%
ISL1902 13 fn7981.2 march 20, 2013 figure 9. oc +leb to out delay figure 10. ac mains to inrush timing figure 11. error amplifer input offset test circuit test waveforms and circuits (continued) oc out oc threshold leading edge blanking oc propagation delay oc + leb to out delay placeholder ac mains inrush t delay t delay 13 14 15 16 17 18 19 20 21 22 23 24 1 2 4 3 5 6 7 8 9 10 11 12 cs+ inrush offref pwmout vref out vdd oc ovp preload ac iout ramp lout lref lfb lpout refin cs- gnd fb2 fb1 deladj verr ISL1902 0.4v 0.1f vdd 470pf 54k 5k 10k 90/140a 90/140a
ISL1902 14 fn7981.2 march 20, 2013 functional description features the ISL1902 led driver is an exce llent choice for low cost, ac mains powered single conversion led lighting applications. it provides active power factor co rrection (pfc) to achieve high power factor using critical conduction mode operation, and incorporates additional feat ures for compatibility with triac-based dimmers. the ISL1902 includes support for both pwm and dc current dimming of the output. similar to the isl1901, the ISL1902 adds additional features to facilitate the design of higher performance led drivers. oscillator the ISL1902 uses a critical conduc tion mode (crcm) algorithm to control the switching behavior of the converter. the on-time of the primary power switch is held virtually constant by the low bandwidth control loop. the off-time duration is determined by the time it takes the current or voltage to decay during the flyback period. when the mmf (magneto motive force) of the magnetic element decays to zero (db/dt=0), the winding voltages collapse and the winding currents are zero (flyback) or dc (sepic). either may be monitored and used to initiate the next switching cycle to achieve crcm operation. additionally, there is a user adjustable threshold, deladj , to delay the initiation of the next switching cycle to allow th e drain-source voltage of the primary switch to ring to a minimum. this allows quasi-zvs operation to reduce capacitive switching losses and improve efficiency. by its nature, the converter operation is variable frequency. there are both minimum and maximum frequency clamps that limit the range of operation. the mi nimum frequency clamp prevents the converter from operating in the audible frequency range while the maximum frequency clam p prevents operating at very high frequencies that may result in excessive losses. an individual switching period is the sum of the on-time, the off-time, and the restart delay duration. the on-time is determined by the control loop error voltage, verr, and the ramp signal. as its name implies, the ramp signal is a linearly increasing signal that starts at zero volts and ramps to a maximum of ~verr/5 - 230mv. ramp requires an external resistor and capacitor connected to vref to form an rc charging network. if verr is at its maximum level of vref, the time required to charge ramp to ~850mv determines the maximum on-time of the converter. ramp is discharged every switching cycle when the on-time terminates. the off-time duration is determined by the design of the magnetic element(s), which depends on the required energy storage/transfer and the inductance of the windings. the transformer/inductor design also determines the maximum on-time that can be supported with out saturation, so, in reality, the magnetic design is critical to every aspect of determining the switching frequency range. the flyback topology the design methodology is simila r to designing a discontinuous mode (dcm) flyback tran sformer with the constraint that it must operate at the dcm/ccm boundary at maximum load and minimum input voltage. the difference is that the converter will always operate at the dcm/ccm boundary, whereas a dcm converter will be more discontinuous as the input voltage increases or the load decreases. for pfc applications, the design is further complicated by the input voltage waveform; a virtually unfiltered rectified ac mains sinewave. once the output power, p o , the output current, i o , the output voltage, v o , and the minimum input ac voltage are known, the transformer design can be started. from the minimum ac input voltage, the minimum average input voltage must be determined. the converter behaves as if the input voltage is an equivalent dc value due to the low control loop bandwidth. p o determines the amount of energy that must be stored in the transformer on each switching cy cle, but must be corrected for efficiency. this includes leakage inductance losses, winding losses, and all secondary side losse s. this can be estimated as a portion of the total efficiency, , or as is typically done, includes all of the losses. a typical minimum operating frequency and maximum duty cycle must be selected. these are somewhat arbitrary in their selection, but do ultimately determine core size. the typical frequency is what occurs when the instantaneous rectified input ac voltage is exactly at the equivalent dc value. the frequency will be higher when the instantaneous input voltage is lower, and lower when the instantaneous input voltage is higher. however, the duty cycle at the equivalent dc input voltage determines the on-time for the entire ac half-cyc le. the on-time is constant due to the low bandwidth control l oop, but the off-time and duty cycle vary with the instantaneous input voltage since the peak switch current follows v = ldi/dt. the lowest frequency may require adjustment once the initial calculations are complete to see if the operating frequency at the peak of the minimum ac input voltage is acceptable. table 1. oscillator definitions v minrms = minimum rms input voltage v maxinrms = maximum rms input voltage f typ(avg) = typical frequency when v in (instantaneous) = v in (rms) =efficiency d max = maximum typical duty cycle desired dmin = minimum typical duty cycle t on(max) =f typ(avg) x d max ls = secondary inductance lp = primary inductance nsp = transformer turns ratio, ns/np ip(peak) = peak primary current within a switching cycle t on on-time of the power fet controlled by out t off off-time duration required for crcm operation t delay = user adjustable delay before the next switching cycle begins p in p o ------ - = w (eq. 1)
ISL1902 15 fn7981.2 march 20, 2013 the first calculation required is to determine the required secondary inductance. the turns ratio n sp is calculated next. knowing the secondary inductance and the turns ratio, the primary inductance can be calculated. with this information, the lowest switching frequency, which occurs at maximum load and at the peak instantaneous input voltage at the minimum rms volt age, can be determined. by setting the maximum duty cycle and picking a typical average frequency, the on-time is already known. the primary peak current at the end of the on-time is: the peak secondary current is the peak primary current divided by the transformer turns ratio. and the off-time is: the lowest switching frequency is the reciprocal of the sum of the on-time, the off-time, and the delay time. the delay time can be approximated if the equivalent drain-source capacitance (c oss ) of the primary switch is known. this value should also include any parasitic capacitance on the drain node. these parameters may not be known during the early stages of the design, but the requ ired delay is typically on the order of 300ns to 500ns. if the lowest frequency does not meet the design requirements, iterative calculations may be required. the highest frequency is determined by the shortest on-time summed with t delay . the shortest on-time occurs at high line and minimum load, and occurs at or ne ar the ac zero crossing when the primary (and secondary) current is zero. the minimum non-zero on-time is ~100ns, suggesting an operating frequency above 1mhz. in any event, the maximum frequency clamp would become active at around 8 00khz. once the primary and secondary inductances are know n, the general formulae to calculate the on-time and off-time at an equivalent dc input voltage are: it is clear from these equations that there is a linear relationship between load current and frequency. at some light load, the frequency will be limited by the maximum frequency clamp. the frequency has an inverse relationship to input voltage and has a less significant affect over a typical operating range. it should be noted, however, that the above equations assume full conduction angle of the ac mains. when conduction angle modulating dimmers are used to block a portion of each ac half-cycle, the switching currents remain essentially unchanged during the conduction portion of the ac half-cycle as the conduction angle is reduced. the result being that the steady state frequency behavior will no t vary much as the conduction angle is reduced from full. if an analog control signal is used instead, the frequency behavior will be as predicted above. the sepic topology the sepic topology, in simplified form, is shown in figure 12. the voltage source indicated may be either dc or rectified ac. the capacitance of c in is negligibly small for applications requiring pfc. the terminology defined in table 1 shall be reused, except ls and lp are replaced by l1 and l2 per figure 12. in steady state operation, the average voltage acro ss l1 and l2 must be zero. if this were not true, saturation would occur. furthermore, this situation implies the voltage ac ross c1 must be equal to the input source voltage, v in . during the on-time, when switch q1 is conducting, the voltage across each inductor is v in . during the off-time, q1 is off, and the voltage across each inductor is -v out . since no dc current may flow through c1, the output current, i o , must be equal to the average current flowing in l2. additionally, i o is also the average current that flows in both inductors during the off-time. to determine the values of l1 and l2, the operating conditions must be defined. the lowest operating frequency occurs at maximum load and minimum input voltage. if operating from and ac source, the lowest frequency occurs at the instantaneous l s v o 1d max ? () 2 ? f typ avg () 2i o ?? ------------------------------------------- - = h (eq. 2) n sp v o 1d max ? () ? v minrms d max ?? ---------------------------------------------------- = (eq. 3) l p l s n sp 2 ------------- = h (eq. 4) t on d max f typ avg () ----------------------- = s (eq. 5) i p peak () v rms 2t on ?? l p ---------------------------------------- = a (eq. 6) i s peak () i p peak () n sp --------------------- - = s (eq. 7) t off l s i s peak () ? v o ------------------------------- - = s (eq. 8) f min 1 t on t off t delay ++ --------------------------------------------------- - = hz (eq. 9) t delay l p c oss c other + () ? ? 2 ----------------------------------------------------------------- s (eq. 10) t off 2l s i o ?? v o ---------------------- - 1 l p n sp v o ?? l s v inrms ? -------------------------------- - + ?? ?? ?? ? = s (eq. 11) t on 2l p n sp i o ?? ? v inrms -------------------------------------- 1 l p n sp v o ?? l s v inrms ? -------------------------------- - + ?? ?? ?? ? = s (eq. 12) figure 12. sepic topology + _ l1 q1 c1 l2 d1 c out c in l o a d
ISL1902 16 fn7981.2 march 20, 2013 peak of the ac voltage waveform at the lowest rms input voltage. therefore, the lowest dc or equivalent dc (rms) input voltage is used as the design point with a corresponding selection of a minimum desired operating frequency. during the on-time, the current in l2 ramps from zero to a peak value, i p . where v in(minrms) is defined as the minimum dc or rms input voltage. during the off-time, the current ramps from i p back down to zero at a rate determined by v out . since the average value of current in l2 must be the load current, i o , equations 13 and 14 can be used to relate the dc or rms input voltage values for t on and t off to i o . equations 15 and 16 may be summed to provide an equivalent switching period for the equivalent dc (rms) input and stated design parameters, and the value for l2 may be calculated. for dc input applications, the calc ulation is straight forward. where t delay is a constant and define d in the next section, ?quasi-resonant switching?. when the input voltage is rectified ac, the desired switching period has to be modified to account for the difference between the rms voltage and the instantaneous peak of the ac waveform. the frequency is lower at the ac peak than at the equivalent dc (rms) input voltage. using equation 19 for t s and substituting into equation 18 yields the appropriate value for l2 in rectified ac input applications. as stated previously, both inductor currents flow to the output during the off-time. i o may be solved for by averaging the sum of both inductor currents during the off-time over a complete switching cycle. using equations 15 and 16 and solving for l1 yields: the final step in specifying the inductor requirements is to determine the dc bias on each inductor. earlier it was assumed that each inductor current ramps from zero to some peak value during the on-time. in reality each inductor has a dc bias current that does not contribute to the output current and may be ignored in the previous calculatio ns, but its value is required to determine the rms currents in each inductor. the reason the dc bias exists is that there can be no dc current through c1 (see figure 12). the current flowing from l2 into c1 during the on- time must equal the current flow ing in the opposite direction from l1 during the off-time. where i c1 is the current through c1 during a complete switching cycle, i dc is the dc bias current, and t s = t on + t off . equation 22 can also be used on a cycle-by-cycle basis providing instantaneous values of t on , t off and v in are used. setting equation 22 equal to zero and solving for i dc yields equation 23, which represents the dc bias current flowing from l1 through c1 into l2 at the equivalent dc (rms) input voltage. it may be thought of as the expected value of bias current. in rectified ac input applications, the bias current varies as needed each switching cycle to balance charge on c1 as the ac voltage varies from valley to peak to valley during each ac half-cycle. quasi-resonant switching the ISL1902 uses critical conduction mode pwm control algorithm. near zero voltage switching (zvs) or quasi-resonant switching, as it is sometimes referred to, can be achieved in the flyback topology by delaying the next switching cycle after the transformer current decays to ze ro (critical conduction mode). the delay allows the primary in ductance and capacitance to oscillate, causing the switching fet drain-source voltage to ring down to a minima. if the fet is turned on at this minima, the capacitive switching loss (1/2 cv 2 ) is greatly reduced. i p v in minrms () t on ? l2 -------------------------------------------------- - = a (eq. 13) i p v out t off ? l2 --------------------------------- = a (eq. 14) t on i o 2l2 ?? v in minrms () ------------------------------------ = s (eq. 15) t off i o 2l2 ?? v out ------------------------ - = s (eq. 16) t s t on t off t delay ++ = s (eq. 17) l2 t s v out v in minrms () ? ? 2i out v out v in minrms () + () ?? ----------------------------------------------------------------------------------------- - = h (eq. 18) t s 2t on t off + () ? t delay + = s (eq. 19) i o v out t off 2 ? 2t on t off + () ? ----------------------------------------- - 1 l1 ------ - 1 l2 ------ - + ?? ?? ? = a (eq. 20) l1 v in minrms () l2 ? v out ----------------------------------------------- - = h (eq. 21) i c1 i dc v out t off 2 ? 2l1t s ?? --------------------------------- v in minrms () t off 2 ? 2l2t s ?? ----------------------------------------------------- - ? + = a (eq. 22) i dc i o v in minrms () v out ? v in minrms () v out + ---------------------------------------------------------- - ? = a (eq. 23) figure 13. sepic waveforms i l2 i l1 v l1, v l2 v in -v out voltage current 0 0 ts t on t off t delay t t
ISL1902 17 fn7981.2 march 20, 2013 the delay duration is set with a resistor from deladj to ground. figure 5 on page 12 presents the graphical relationship between the delay duration and the value of the deladj resistance. the relationship is linear for resist ance values greater than ~ 20k ? and can be estimated using equation 24. soft-start operation soft-start is not user adjustable and is fixed at ~350ms. both the duty cycle and control loop reference have soft-start. this ensures a well behaved closed loop soft-start that results in virtually no overshoot. biasing the ISL1902 has a nominal v dd start and stop threshold of 15.5v and 7.1v, respectively. the wi de hysteresis allows resistive trickle charging from the high voltage input for start-up bias. operating bias is then supplied fr om another source, such as an auxiliary transformer winding or in the case of a non-isolated design, directly from the output or from a tap in the led string. the v dd bypass capacitance value is critical to a successful design. unless there is a dc source available, such as the output, the v dd capacitance must be able to store enough energy to provide bias during the ac voltag e valleys and, if used with a dimmer, provide bias when the dimmer is blocking the ac voltage each half-cycle. ac detection and reference generation the ISL1902 creates a 0v to -0.5v reference for the led current control loop (ea reference) by di rectly measuring the conduction angle of the ac input voltage. the reference changes only with conduction angle and is virtually unaffected by variation in either voltage amplitude or frequency. the ISL1902 is compatible with both leading and trailing edge modulated dimmers. the ISL1902 detects the conduction angle using a divider network across the ac line and connected to the ac pin, although it can also be located after the ac bridge rectifier. figure 14. quasi-resonan t near-zvs switching winding current fet d-s voltage t delay 73.33 10.2 r deladj k () ? + ns (eq. 24) figure 15. trickle charge start-up w/aux. winding vdd 124 ISL1902 r1 c1 cr1 cr2 rectified ac+ rectified ac- figure 16. linear regulator start-up w/aux. winding vdd 124 ISL1902 r2 c1 cr2 rectified ac+ rectified ac- r1 vr1 q1 cr1 emi filter 1 2 4 3 ac 19 20 21 22 23 24 gnd ISL1902 figure 17. ac detection
ISL1902 18 fn7981.2 march 20, 2013 the advantage to sensing the ac voltage directly, rather than the rectified voltage, is that there is no error in detecting the ac zero crossing. if monitored after the ac rectifier bridge, the ac signal tracks the filter capacitor voltage, which may not discharge in phase with the ac voltage. this ca n lead to incorrect detection of the ac zero crossing. at light lo ad, the filter capacitor may not fully discharge before the ac voltage begins to increase again, resulting in no detection of the ac zero crossing at all. the ac pin and has a usable input range of 0v to 4v. the peak of the input signal should range between 1v and 4v for uncompromised accuracy. the ac detection circuit measures both the duration of the ac conduction angle and half-cycle duration. by comparing them every half-cycle, the detection circuit creates a frequency independent reference that is updated each ac half-cycle. the reference generated by the ac detection circuit is available as the lpout signal. here it can be modified, or not, and connected to refin for setting the control loop reference. examples of modification includ e interfacing with an external transducer, such as an ambient li ght sensor (als) or temperature sensor (ntc or ptc) to modify the reference based on the sensor input. the ISL1902 also supports analog dimming control by allowing the control loop reference to be connected to refin, bypassing lpout completely. ac may be directly coupled to a 90hz to 130hz pwm signal to generate a reference if dimming is desired without using an ac dimmer, or an independent reference may be input to refin with lpout not connected. in the event of an ac outage, the ac mains frequency reference is lost. the ISL1902 will force the reference to zero volts and reset the soft-start circuit appr oximately 35ms after the last ac zero crossing is detected. if ac is held above its detection threshold for more than 35ms, the internal reference is forced to its maximum of 0.5v. figure 18. alternate ac detection emi filter 1 2 4 3 ac 19 20 21 22 23 24 gnd ISL1902 figure 19. alternate configurations for the control loop reference 6 8 9 10 11 12 lpout refin 13 14 15 16 ISL1902 5 4 3 vref 6 8 9 10 11 12 lpout refin 13 14 15 16 ISL1902 5 4 3 vref 6 8 9 10 11 12 lpout refin 13 14 15 16 ISL1902 5 4 3 vref analog or pwm control figure 20. using an ambient ligh t sensor with an ac line dimmer 6 8 9 10 11 12 lpout refin 13 14 15 16 ISL1902 5 4 3 vref 17 18 19 lfb lref lout als figure 21. using an ambient li ght sensor with analog or pwm input 6 8 9 10 11 12 lpout refin 13 14 15 16 ISL1902 5 4 3 vref 17 18 19 lfb lref lout als analog or pwm control
ISL1902 19 fn7981.2 march 20, 2013 current sensing the ISL1902 is configured to re gulate the output current by differentially monitoring the ou tput switching current using the cs+ and cs- pins. the output switching current waveform is amplified 4x and output on iout where it must be scaled and filtered before being input to the control loop at the fb pin. the required filter time constant depends on the compensated error amplifier bandwidth. the filter bandwidth must be higher than the control loop bandwidth, typically an order of magnitude higher, but it is generally not necessary to filter the iout signal to form a nearly dc voltage. the compensated error amplifier performs that function. the oc pin provides cycle-by-cycle overcurrent protection. the output fet drive signal out is terminated if oc exceeds 0.6v nominal. there is ~120ns of leading edge blanking (leb) on oc to minimize or eliminate external filtering. dimming the ISL1902 supports both pwm and dc current modulation dimming. dc current dimming is the lower cost method, but results in a non-linear dimming characteristic due to the increasing efficacy of the leds as current is reduced. pwm dimming results in linear dimming behavior. an external fet, controlled by pwmout, switches the led current on and off to achieve pwm dimming. in either case, the control loop determines the average current delivered to the load. it does not matter if the load current is dc or pulsed, the converter output capacitance and control loop operate to filter and average the converter output current independently of the actual load current waveform. the dimming pwm and control loop are linked together such that the pwm duty cycle tracks the main control loop reference setpoint. if the control loop is set for 50% load, for example, the dimming pwm duty cycle is set for 50%. the led current will be at 100% load for 50% of the time and 0% load for 50% of the time, which averages to the 50% average load setpoint. see figure 6 for a graphical representation of the relationship between refin and pwmout duty cycle. it should be noted that the pwmout duty cycle is not allowed to go to zero. there is a minimum on-time that ensures the led string is not allowed to become a continuos open circuit. aside from tracking the main co ntrol loop reference, the pwm dimming control is open loop, but is nevertheless self regulating. there is no closed loop feedback to regulate the load current during pwm conduction as is th e case with most pwm dimming methods. if the average current into and out of the output capacitor is not equal, the output voltage will change, increasing or decreasing with the polarity of the charge imbalance. the forward voltage characteristic of the leds will cause the current to increase or decrease with th e change in output voltage until the average capacitor current returns to zero. figures 24 and 25 show a simulation schematic and results, respectively, illustrating the pwm dimming behavior for a 50% loaded condition. the converter output is idealized and represented as a 50ma dc current source and the pwm is operating at 50% duty cycle. figure 22. alternate method for using pwm input control with an ambient light sensor 6 8 9 10 11 12 lpout refin 13 14 15 16 ISL1902 5 4 3 vref 17 18 19 lfb lref lout als 20 ac 100/120hz pwm control figure 23. temperature compen sating the reference using an ntc 6 8 9 10 11 12 lpout refin 13 14 15 16 ISL1902 5 4 3 vref 17 18 19 lfb lref lout 20 ac r ntc figure 24. pwm dimming simulation schematic pwm duty cycle c out figure 25. pwm dimming results v y2 11.68 11.70 11.72 11.74 11.76 11.78 11.80 11.82 11.84 11.86 time/ms 1ms/div 500 501 502 503 504 505 506 ma y1 -0 20 40 60 80 100 pwm load current v out converter i o
ISL1902 20 fn7981.2 march 20, 2013 the red trace is the current source supplying the output. the blue trace is the output capacitor volt age. the green trace is the led current. when the pwm signal is off, the 50ma current source charges c out and the output voltage increases. when the pwm turns on, 100ma of current flows th rough the leds, with the initial current slightly higher and the fi nal current slightly lower as c out discharges. the peak-to-peak ripple voltage on c out is ~160mv. the decrease in the led current du ring conduction is determined by the size of the output capacitor and the led current. linear amplifier the linear amplifier block is a fully accessible uncommitted operational amplifier. it may be used for a variety of purposes, such as interfacing sensors, direct sensing of led current, or a pre-load amplifier. examples of using the linear amplifier as a sensor interface are shown in figures 20 through 23. the linear amplifier may be used as a pre-load control to provide a larger dynamic dimming range as well as providing additional holding current for applications using triac-based dimmers. as shown in figure 26, the pre-load can be configured as an active load that increases linearly as the control loop reference level (refin) decreases. the result is no t only is the total load current decreased as refin is lowered, but an increasing portion of the load current is shunted to the pre-load. at some point, the preload conducts all of the load current while allowing zero led current. this allows the conver ter to continue operation to maintain circuit bias with zero led current. very high levels of led dimming resolution become achievable. both the maximum pre-load current and turn-o n threshold are adjustable. again referring to figure 26, th e voltage across r5 represents the current flowing in the pre-load. the maximum level of this signal is limited by the voh of the linear amplifier and the gate threshold voltage of the pre- load fet, q1. a reasonable maximum voltage for this signal is 3.0v. therefore, the maximum pre-load current, i pl , is 3.0/r5. where lref and refin are the voltages at the lref and refin pins, respectively. for purposes of illustration, if r3 and r4 are equal, equation 25 simplifies to: equation 26 shows that if refin is greater than 2x lref, v o is non-positive and the pre-load is not conducting. with proper selection of lref and r3/r4, th e pre-load turn-on threshold and gain characteristics can be matched to the application requirements. where%h is the selected fraction of maximum load when the pre- load begins to conduct. as an example, assume the pre-lo ad should begin to operate at 75% of full load, and that th e maximum pre-load current, i pl , is 50ma. using equation 27 to solve for the ratio of r3/r4 yields a result of 8. equation 28 yiel ds a value of 0.333v for lref. remembering the maximum allowed voltage across r5 is 3.0v yields r5 = 3.0v/50ma = 60 at 150mw. v o is plotted in figure 27. alternatively, the linear amplif ier may be used to control a second led string, either to force current sharing, or to control a colored led string for color correc tion. the second string can be controlled from the same reference as the first led string allowing the string currents to trac k, or it can be controlled from a separate reference that allows the two strings to work in opposition, sharing the load current in proportion to each reference. figure 28 shows the tracking configuration. figure 26. linear amplifie r configured as pre-load + vref 1 2 4 3 5 6 7 8 9 10 11 12 preload lout lref lfb lpout refin 13 14 15 16 17 18 19 20 21 22 23 24 r1 r2 r3 r4 r5 ISL1902 q1 v o v r5 lref 1 r3 r4 ------- - + ?? ?? ? r3 r4 ------- - refin ? ?? ?? ? == v (eq. 25) v o v r5 2lref ? refin ? == v (eq. 26) r3 r4 ------- - 30.5%h ? () ? 0.5 %h ? 3 ? () 2 6%h ? + %h -------------------------------------------------------------------------------------------------------------- - = (eq. 27) lref r3 r4 ------- - 0.5 %h ?? 1 r3 r4 ------- - + -------------------------------------- vref r2 r1 r2 + ---------------------- ? == v (eq. 28) figure 27. pre-load example 0 1.0 1.5 2.0 2.5 3.0 0 50 100 150 200 250 300 350 400 450 500 refin (mv) v o (v) 0.5
ISL1902 21 fn7981.2 march 20, 2013 the linear amplifier may also be used to measure and scale the led current directly rather than using the differential current sensing inputs, cs+ and cs-, that measure the switching current. amplifying the signal allows a smaller sensing resistor value for improved efficiency. as shown in figure 29, the voltage across r4 is scaled by the linear amplifier with a gain of 1 + r2/r1. control loop the control loop configuration is us er adjustable with selection of the external compensation components. for applications requiring power factor correction (pfc), a very low bandwidth integrator is used, typically 20hz or less. in other applications, the control loop bandwidth can be increased as required, like any other externally compensated voltage mode pwm controller. the ISL1902 has two error ampl ifiers that share a common non-inverting input and a common output. each ea can sink current, but has negligible sourcing capability. an external pull-up resistor to vref is required. this configuration causes the ea with lowest output to be dominant. ea1 is the principal error amplifier and is compensated externally for low bandwidth for pfc applications. the downside to a lo w bandwidth amplifier is that it cannot respond to input transients quickly. this is where the second ea comes in. it can be configured for a much higher bandwidth so that transient resp onse is greatly improved. under normal operating conditions ea 2 is not active. its feedback network is set for a higher output than ea1. when an input surge occurs, ea1 cannot respond rapidly and the surge propagates to the output. ea2 becomes active when its feedback voltage exceeds the reference setpoint an d acts to reduce the output transient. the difference in setpoint is accomplished by weighting the feedback networ ks to the eas appropriately. the voltage on iout is a scaled version of the cs+/cs- differential signal, having been amplified by 4x. when averaged, it is a scaled representation of the converter output current, i o . by measuring iout in this manner, both average and instantaneous inductor currents are known. the instantaneous inductor current information informs the critical conduction mode (crcm) oscillator when the switching current has decayed to zero. figure 30 shows a typical configur ation for the control loop. the sensing resistor r s determines the amplitude of the cs+ signal. at maximum load this signal must be scaled to match the 0.5v maximum reference. since iout is 4x the amplitude of the cs+ signal, a simple resistor divider wi th filtering is required to scale iout prior to connecting to the fb input. where a iout is the iout buffer gain (nominally 4x), a divider is the gain of the external resistor divider on iout (r2/(r1 + r2)), v ref is the maximum reference level (0.5v), and i o is the maximum output current. in most applications, r s will be sized to minimize power dissipation while providing adequate signal level. the minimum value of the i o r s product is 125mv, required to achieve 0.5v on iout. figure 28. second led string control + 1 2 4 3 5 6 7 8 9 10 11 12 lout lref lfb lpout refin 13 14 15 16 17 18 19 20 21 22 23 24 r3 r5 ISL1902 q1 c1 figure 29. direct led current sensing + 6 7 8 9 10 11 12 lout lref lfb fb1 13 14 15 16 17 18 19 r2 r4 ISL1902 r1 r3 = r1||r2 r s v ref a iout a divider i o ?? ------------------------------------------------------------ = (eq. 29)
ISL1902 22 fn7981.2 march 20, 2013 in applications requiring pfc, th e fast loop bandwidth can be set to react to line transients without affecting steady state operation. for example, the slow loop requires iout to be filtered with a time constant of 50ms to 100ms. the fast loop (to be effective), requires less filtering on iout and requires a bandwidth three orders of magnit ude (1000x) higher with a 60% divider weighting compared to the slow loop (taking into account the peak-to-average ratio of a sinusoid). ovp the ISL1902 has independent overvoltage protection accessed through the ov pin. there is a nominal 20a switched current source used to create hysteresis. the current source is active only during an ov fault; otherwise, it is inactive and does not affect the node voltage. the magnitude of the hysteresis voltage is a function of the external resistor divider impedance. if the divider formed by r1 and r2 is sufficiently high impedance, r3 is not required, and the hysteresis is: if that does not result in the desired hysteresis then r3 is needed, and the hysteresis is: if the ov signal requires filtering, the filter capacitor, c opt , should be placed as shown in figure 17. the current hysteresis provides great flexibility in setting the magnitude of the hysteresis voltage, but it is susceptible to noise due to its high impedance. if the hysteresis was implemented as a fixed voltage instead, the signal could be filtered with a small capacitor placed between the ov pin and signal ground. this technique does not work well when the hysteresis is a current source because a current source takes time to charge the filter capacitor. there is no instantaneous change in the threshold level rendering the current hysteresis ineffective. to remedy the situation, the filter capacitor must be separated from the ov pin by r3. the capacitor and r3 must be physically close to the ov pin. offref control the ISL1902 provides the ability to disable the output based on the level of the control loop reference, refin. setting offref to a voltage between 0 and 0.6v determines the threshold voltage that disables the output. offref allows the designer to disable the output at a predetermined load current to prevent undesirable behavior, such as at light loading conditions when there may be insufficient current to maintain the holding current in a triac-based dimmer. se tting offref to less than 100mv disables this feature. offref has a nominal hysteresis of 50mv. figure 30. control loop configuration differential cs - iout processor + _ cs- iout fb1 ac reference generator r1 r2 c f1 c fb2 r fb1 vref r pu ISL1902 r s verr lpout refin + _ fb2 r fb2 c fb1 c f2 r3 r4 cs+ ea1 ea2 figure 31. iout filtered waveforms (100hz) filtered iout fast loop filtered iout slow loop time/ms 2ms/div 0 2 4 6 8 10 12 14 normalized volts (v) 0 0.2 0.4 0.6 0.8 1.0 1.2 iout filtering figure 32. ov hysteresis + _ 20a vref 1 0 monitored voltage r1 r2 r3 c opt 1.5v v ov ri g sin () 1.5 r1 r2 + () r2 -------------------------- - ? = v (eq. 30) v2010 6 ? r1 ?? = v (eq. 31) v2010 6 ? r1 r3 r1 r2 + () r2 -------------------------- - ? + ?? ?? ?? = v (eq. 32) refin off () offref 0.100 ? = v (eq. 33)
ISL1902 23 fn7981.2 march 20, 2013 preload signal preload is a digital signal used to control an external fet that discharges the output capacitanc e if ac is low for more than ~30ms, or if refin drops below the offref threshold. this feature prevents the output capacitor from providing load current for an extended period of time after the converter is disabled. otherwise, the output will dim as the output capacitance slowly discharges through the leds. this process can take a significant amount of time, resulting in ?a fterglow?, unless supplemental discharge methods are used. the advantage of preload over a non-switched resistive load is ef ficiency improvement. examples of preload usage may be found on pages 5 through 7 in the ?typical applications?. in-rush control the ISL1902 features a ac half-cycle-by-half-cycle in-rush control signal. due to the capacitive input of dc/dc converters operating with a leading edge modulated ac line dimmer, there is an input current spike every half-cycle when the ac line dimmer turns on, particularly so when conduction begins near the ac peak. the current spike is normally attenuated with a resistor in series with the ac line. the resistor is always present and dissipates power even at full dimmer conduction. the ISL1902 provides a control signal, inrush, which may be used to gate an external switch, such as a triac to bypass the in-rush limiting resistor after the in-rush event is over. the signal is low when the ic detects the absence of ac line voltage. when enabled, approximately 150s after ac voltage is detected, in-rush outputs an 80khz square wave. this may be coupled through a pulse transformer or other isolation device to allow control of a level shifted device. examples of using inrush can be found in the ?typical applications? on pages 5 and 7. another example is shown in figure 33. gate drive the ISL1902 output is capable of sourcing and sinking 1.5a. the typical on-resistance of the outputs is 12 ? . the out high level is limited to the out clamp voltage or v dd , whichever is lower. thermal protection internal die over-temperature protection is provided. an integrated temperature sensor protects the device should the junction temperature exceed +150c. there is approximately +25c of hysteresis. ground plane requirements careful layout is essential for satisfactory operation of the device. a good ground plane must be employed. v dd and vref should be bypassed directly to gnd with good high frequency capacitance. figure 33. inrush example using a photo-triac emi filter ac inrush
ISL1902 24 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7981.2 march 20, 2013 for additional products, see www.intersil.com/en/products.html about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the fastest growing markets wi thin the industrial and infrastructure, personal computing and high-end consumer markets. for more inform ation about intersil or to find out how to become a member of our winning team, visit our website and career page at www.intersil.com . for a complete listing of applications, re lated documentation and related parts, plea se see the respective product information page. also, please check the product information page to ensure that you have the most updated datasheet: ISL1902 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff reliability reports are available from our website at: http://rel.intersil.com/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change march 20, 2013 fn7981.2 initial release.
ISL1902 25 fn7981.2 march 20, 2013 package outline drawing m24.15 24 lead shrink small outlin e plastic package (qsop/ssop) 0.150? wide body rev 3, 2/13 notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m-1982. 3. package length does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. package width does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. terminal numbers are shown for reference only. 7. lead width does not include dambar pr otrusion. allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of ?b? dimension at maximum mate- rial condition. 8. controlling dimension: millimeter. index area 24 1 -b- 0.17(0.007) ca m bs -a- m -c- seating plane 0.10(0.004) x 45 0.25 0.010 gauge plane 3.98 3.81 6.19 5.80 4 0.25(0.010) b m m 1.27 0.41 0.49 0.26 5 8 0 1.54 0.25 0.18 8.74 8.55 3 1.75 1.35 0.25 0.10 0.30 0.20 7 0.635 bsc 5.59 4.06 7.11 0.635 detail ?x? side view 1 typical recommended land pattern top view side view 2 5 0.38

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